The integration of a large number of components upon a single chip requires the formation of sophisticated interconnects. The interconnects should be formed with minimal signal delays and optimal packing density, in accordance with the principles enunciated in "On-Chip Wiring for VLSI: Status and Directions" by M.B. Small and D.J. Pearson, IBM J. Res. Develop., Vol. 34, No. 6 (11/6/90) pp. 858-867.
To achieve the above objectives, the preferred interconnect material is copper. Copper provides a number of advantages for wiring applications including low resistivity and a high melting point.
At present, aluminum is the material used in fabricating interconnects on most integrated circuits. This invention seeks to replace the aluminum with copper in the fabrication of advanced integrated circuits and ultra-fast logic devices.
As previously mentioned in the aforesaid U.S. patent application Ser. No. 07/790,971, the use of copper as an interconnection material presents several problems, such as (1) copper oxidizes easily at low temperatures; (2) copper has poor adhesion to substrates; (3) copper has a high diffusion in silicon dioxide and other dielectric materials used in micro-circuitry; (4) copper has a low reaction temperature with most silicides; and (5) copper requires a high temperature for patterning by reactive ion etching (RIE).
In order to overcome these disadvantages when using copper as an interconnect material, it is necessary to passify the copper surfaces and provide diffusion barriers between the copper and the adjacent layers.
It has been proposed in the aforementioned U.S. patent application Ser. No. 07/790,971, to TiN-encapsulate the copper fine line structure by annealing the copper-titanium alloy lines in an NH.sub.3 ambient. This technique is very versatile because a barrier layer can be formed simultaneously on all exposed surfaces of the copper lines.
A number of limitations to the above method have been discovered, however, particularly when forming fully-planar copper lines by filling grooves in a dielectric and removing the excess. In this case, the copper alloy must be deposited into a feature without leaving a void, so electroplating or chemical vapor deposition is required. It is difficult to deposit refractory metal-copper alloys, such as copper-titanium, with electroplating or chemical vapor deposition techniques. Additionally, any residual titanium in the copper lines increases the resistivity above that of pure copper.
The present invention discloses a self-aligning process for capping the copper lines without the need for deposition of a copper alloy (such as copper-titanium).